Alternitive to sceKernelIcacheInvalidateAll

[m0skit0]

IIRC both caches are the same size.

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[wth]

IIRC both caches are the same size.

hm well according to http://en.wikipedia.org/wiki/R4000
"The R4000 was a scalar superpipelined microprocessor with a eight-stage integer pipeline. During the first stage (IF), a virtual address for an instruction is generated and the instruction translation lookaside buffer (TLB) begins the translation of the address to a physical address. In the second stage (IS), translation is completed and the instruction is fetched from an internal 8 KB instruction cache. The instruction cache is direct-mapped and virtually indexed, physically tagged. It has a 16- or 32-byte line size. Architecturally, it could be expanded to 32 KB."

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[Davee]

IIRC both caches are the same size.

hm well according to http://en.wikipedia.org/wiki/R4000
"The R4000 was a scalar superpipelined microprocessor with a eight-stage integer pipeline. During the first stage (IF), a virtual address for an instruction is generated and the instruction translation lookaside buffer (TLB) begins the translation of the address to a physical address. In the second stage (IS), translation is completed and the instruction is fetched from an internal 8 KB instruction cache. The instruction cache is direct-mapped and virtually indexed, physically tagged. It has a 16- or 32-byte line size. Architecturally, it could be expanded to 32 KB."

PSP uses Allegrex.

[m0skit0]

Davee's answers as usual: pretty short Like scottish kilts

What he means is that PSP uses a custom MIPS and so such references are pretty much useless. This is an outdated, but more reliable reference.

[wth]

ok
also then according to http://en.wikipedia.org/wiki/PlayStatio ... e_hardware
"Both CPUs contain 16 KiB of two-way set associative instruction cache and data cache respectively."
So if I understand correctly that means a 32KB cache with 16KB Dcache / 16KB Icache no

[RNB_PSP]

How about using an uncached pointer(or jumping to an uncached function pointer)? Will that bypass the cache? That will be a huge performance hit but will ensure your code works properly.

[m0skit0]

The MIPS CPU will fetch code from the instruction cache, which is not updated if you use uncached pointers, and thus your code will not run.

[RNB_PSP]

The MIPS CPU will fetch code from the instruction cache, which is not updated if you use uncached pointers, and thus your code will not run.

Oh, I see. Thanks. I thought using an uncached pointer will make the cpu behave as if the cache(s) doesn't exist.

[m0skit0]

You can skip data cache to read/write, but the CPU will always fecth instructions from cache.